eispice is an open-source clone of the classic Berkeley SPICE 3 simulation engine designed specifically for board-level Signal Integrity (SI) verification.
While traditional Berkeley SPICE was created to simulate integrated circuits (ICs) at the transistor level, it fails to address high-speed printed circuit board (PCB) layouts efficiently. Traditional SPICE tools are notoriously slow and lack native compatibility with high-speed component models. eispice addresses these limitations by shifting the simulation focus from internal silicon to the PCB interconnect layer. 🚀 Key Optimization Features for High-Speed PCBs
eispice modifies and expands the core Berkeley SPICE 3 architecture to optimize high-speed digital designs: 1. Native IBIS Model Support
The Problem: Traditional SPICE uses complex, proprietary transistor models (like BSIM). IC manufacturers rarely share these models to protect their intellectual property.
The eispice Solution: It natively parses and simulates Input/Output Buffer Information Specification (IBIS) models. IBIS models use behavioral data tables rather than transistor math. This keeps manufacturer IP secure while offering rapid simulation speeds. 2. Advanced Transmission Line Modeling High Speed PCB Simulation Techniques – Terasic
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